(Junior) Testmanager Systemintegration (m/f/d)

To raise technologies to the next level, face challenges and work on the innovations of tomorrow - for this we need FERCHAU Expert: both as a (Junior) test manager system integration (m/w/d) that we want to bring technologies to the next level. We implement exciting projects for well-known OEMs and automotive suppliers and take responsibility for complex development projects. Do you want to fully develop your potential? We offer you an environment with diverse tasks, new challenges and permanent opportunities, where you can continue to grow and sharpen your profile.

(Junior) Siegen This will be your job planning, coordination and monitoring of all test activities based on defined system requirements Development of test strategy and test plans at system level (SYS.4) Preparation and execution of test cases for system and integration tests as well as coordination with interface partners (SYS.2 and SWE.6) Application of the Software-in-the-Loop (SiL) kit for simulation and testing Use of additional Vector tools to analyze and automate test processes Implementation of hardware-in-the-loop (HiL) tests taking into account the ASPICE process requirements Evaluation and documentation of test results and derivation of approval recommendations This is what awaits you with us security through an indefinite contract Much flexibility through sliding time controls and the ability to work mobile Professional and personal development possibilities We offer special holidays, kindergarten grants, anniversary grants etc. Networking and just having fun with regular team events

You bring this with completed engineering studies in the field of electrical engineering, mechatronics or physics Experience in the planning, implementation and control of system tests Routinized handling of CANoe, vTestStudio and CAPL for system integration testing First experiences with SiL Kit Vector desirable Experience in the development and documentation of test strategies for system level (SYS.4) Experience in carrying out residual bus simulations