Group Leader Advanced Digital ASIC & FPGA Design

A central part of your role is the professional and disciplinary leadership of a growing team. You provide technical guidance, support as an experienced Sparring partner and enable space for exchange and qualification. You coordinate the project landscape of your group so that resources are used meaningfully and your employees can concentrate on their professional work and thus provide excellent research results. With a clear view for schedules, budgets and milestones, you can also manage your own larger projects as project manager. Beyond the day-to-day business, drive forward the strategic development of your group. You observe technological trends and market needs, identify new potentials and translate them into future-oriented research topics in the field of digital integrated systems. Together with our business fields, You acquire new research and development projects. To do this, you will specifically address potential industrial customers or form consortia to develop public project applications (e.g. BMFTR, EU). For active networking, you will represent your group at trade fairs, conferences and workshops and present research results, ideas and cooperation offers.

Minimum qualifications: Graduate degree (M. Sc. or Uni-Diplom), with doctoral degree, in electrical engineering or technical computer science Experience in the development of digital integrated circuits and systems for ASIC solutions under 45 nanometers and in the management of research or development projects Knowledge of digital circuit design, SoC architectures and/or hardware accelerators Safe handling of development tools for digital ASIC and FPGA development, such as the Cadence Digital Design Flow or the AMD Vivado Design Suite Constructive, forward-looking attitude and the claim to actively shape the further development of the group Structured and forward-looking working to efficiently orchestrate projects and resources, enable focus and create a reliable working environment for the team Safe prioritization and coordination in German and English to clearly represent interests, to make decisions based and to ensure consistent cooperation with higher-level project structures. Required qualifications: Experience in FPGA design Experience in the acquisition of industrial projects

You actively shape the content of your group – from the topic finding to the project landscape to the strategic development of new research fields (e.g. Chiplets, PIC). Various possibilities for professional and personal development, including through targeted training and exchange in scientific and industrial networks Flexible working hours (running time with integrated core working time from 9:30 to 15:00, Friday from 9:30 to 13:00) and mobile work up to two days a week for a better reconciliation of work and private life Occupational pension (VBL) and grant to the Deutschland-Ticket Job Very good transport connection with ÖPNV/car (bus stop at 50 m distance, motorway connection Kreuz Kaiserberg) as well as free parking and lockable bicycle parking for employees Free precautionary offers such as annual influenza vaccination or visual testing Family and Occupational Compatibility Support: Mit-Kind-Office, Kindernotpflege und Beratungs zu Homecare-Eldercare etc. in cooperation with the pme family service Corporate Benefits: discounted offers of well-known manufacturers and brands