0PhD student in AI hardware architecture: Cache computing for LLMs (FPGA & ASIC)
Fraunhofer-Institut für Mikroelektronische Schaltungen und Systeme IMS | Germany | 47xxx Duisburg | Full time / Home office | Published since: 27.05.2026 on stepstone.de

PhD student in AI hardware architecture: Cache computing for LLMs (FPGA & ASIC)

Branch: Humanities Branch: Humanities


The Fraunhofer Society is one of the world's leading organisations for application-oriented research. 75 institutes develop groundbreaking technologies for our economy and society – more precisely: 32 000 people from technology, science, administration and IT. You know, who comes to Fraunhofer wants and can change something. For yourself, for us and the markets of today and tomorrow. The research group “System on Chip” at Fraunhofer IMS develops energy-efficient AI accelerators based on RISC-V from RTL design to FPGA prototypes to ASIC implementation. In close cooperation with the University of Duisburg-Essen (chair Electronic Components and Circuits), we have already successfully conducted several chip-tapeouts and publish them regularly at international conferences. Your mission: In the German-Taiwanesian research project STICAM (Secure Transformers in Cache Memory), you will explore a completely new architecture class – so-called Compute-in-Cache architectures – that will make large voice models (LLMs) data-protection-compliant and executable with only 1–5 Watt directly on edge devices. Their results provide the basis for applications in smart health, robotics and safe human-machine interaction to work without cloud connection in the future – a decisive advantage for data protection, latency and energy efficiency. .

Your tasks • Your profile • What we offer

You develop the state of science for cache-centric accelerator architectures, processing-in-memory and transformer interference under resource constraints. This will guide you to open research questions for your dissertation. You develop formal models that describe the trade-off between memory and computational function in reconfigurable cache architectures. In doing so, you identify fundamental efficiency limits (energy, latency, area) and derive design principles from them. To do this, use Python-based modeling frameworks as well as cycle-curate simulations. After that, transfer your architecture concepts into synthesizable RTL (Verilog/VHDL) and validate them on Xilinx/AMD-FPGAs in our laboratory. You work in the context of a RISC-V-based SoC and collect real measurement data (performance, energy consumption) to verify your analytical models. In regular project meetings (approximately monthly) and during research stays in Taiwan, you agree with the partners and integrate your results into the overall system. In the long term, prepare an ASIC implementation together. You publish your results at international conferences (e.g. DATE, DAC, ISSCC) and in professional journals. In addition, supervise Bachelor/Master's and Student Assistants who work on aspects of your topic.

Minimum qualification: Very well completed scientific studies (Master/Uni Diploma) in electrical engineering, computer science, technical computer science, physics with very good grades Practical experience in digital hardware design, especially RTL design with VHDL or SystemVerilog Basic knowledge of computer architecture, in particular cache hierarchies, storage systems and/or processor design Very good knowledge of German and English for cooperation in an international environment Required qualifications: Experience with RISC-V architecture or processor design First practical experience with FPGA implementations, preferably on Xilinx/AMD platforms Knowledge in the field of AI hardware accelerators, transformer architectures or processing-in-memory Basic knowledge of ASIC design flows (synthesis, place & route, timing analysis) Programming skills in Python and/or C/C++ for modeling and automation

Doctorate within 3 years in an application-oriented topic at the interface of computer architecture, AI hardware and edge computing. You can access institute-owned FPGA laboratories, EDA toolchains and simulation infrastructure for your practical work. Teaching obligations will not be transferred to you. The doctoral degree is awarded by the University of Duisburg-Essen. As part of the international STICAM project, you will participate in multi-week research stays at the Taiwanese partner institutions and publish them at international conferences. In addition to the support provided by an institute-internal specialist, a regular organized exchange takes place on the scientific state of your work within the framework of a doctorate/paternal body. During the promotion period, you will be supported by accompanying offers. For example, you can benefit from regular doctoral student coaching and learn to safely apply professional methods of project management during your doctorate and to support the project acquisition. If the dissertation is submitted in due time, the option is to further deepen the research work within the framework of a connection agreement or to switch to other areas. The full-time post as a doctoral student with half-remuneration provides 50% of the time for your doctoral degree and 50% for cooperation in research projects as a scientific assistant. Flexible working hours (running time with integrated core working time from 9:30 to 15:00, Friday from 9:30 to 13:00) and mobile work on up to two days a week for better reconciliation of work and private life Occupational pension (VBL) and grant to the Deutschland-Ticket Job Very good transport with public transport/car and free parking and bicycle parking for employees Family and Occupational Compatibility Support: Mit-Kind-Office, Kindernotpflege und Beratungs zu Homecare-Eldercare etc. in cooperation with the pme family service Corporate Benefits: Benefits Offers from renowned manufacturers and brands

Location

ava Fraunhofer-Institut für Mikroelektronische Schaltungen und Systeme IMS
47057  Duisburg
Germany

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