Junior Test Engineer Electronics / Verilog (mwd)

You're a graduate or a junior? Then come on board a steadily growing medium-sized Munich company, which has won several awards for its innovations!

As a Junior Test Engineer Electronics / Verilog, you will be carefully and comprehensively involved in the verification of an exciting, completely newly developed product and the optimization of the verification environment. You work on the design and implementation of tests with SystemVerilog UVM and SystemC. Also perform simulations and analyze test and simulation results. You work closely with the design team and support the commissioning of new devices in the laboratory environment.

(Fach) Graduate of a suitable technical discipline First experience in the course of studies and/or relevant internships or Working student activities in Germany in the digital verification with SystemVerilog or UVM as well as cooperation in the design of tests, test setups and test plans SystemC experience is desirable, but no need Knowledge of working with Linux as an operating system and with a script language such as Python or Perl Ideally experience in digital design and with object-oriented C++ Of advantage, but explicitly no need, are knowledge of common video interfaces such as VDS, HDMI, DSI, CSI or DisplayPort, as well as data interfaces such as PCI and AXI Good knowledge of German and English

You work in a very successful company that is a direct supplier of the automotive industry with a mature electronic product.

You can expect: design and learning opportunities Very good transport connection (near S-Bahn station and bus stops) and parking for staff, bike leasing, home office Very good working environment, flat hierarchies 30 days off Good pay according to experience Stable, growing company Takeover of moving costs JOBV1_EN